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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Automatic Construction of Checking Circuits Based on Finite Automata
Matušová, Lucie ; Strnadel, Josef (referee) ; Kaštil, Jan (advisor)
Cílem této práce bylo studium aktivního učení automatů, navržení a implementace softwarové architektury pro automatickou konstrukci hlídacího obvodu dané jednotky implementované v FPGA a ověření funkčnosti hlídacího obvodu pomocí injekce poruch. Hlídací obvod, tzv. online checker, má za úkol zabezpečovat danou jednotku proti poruchám. Checker je konstruován z modelu odvozeného pomocí aktivního učení automatů, které probíhá na základě komunikace se simulátorem. Pro implementaci učícího prostředí byla použita knihovna LearnLib, která poskytuje algoritmy aktivního učení automatů a jejich optimalizace. Byla navržena a implementována experimentální platforma umožňující řízenou injekci poruch do designu v FPGA, která slouží k otestování checkeru. Výsledky experimentů ukazují, že při použití checkeru a rekonfigurace je možné snížit chybovost designu o více než 98%.
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Web Portal for VHDL Core Generator
Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
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Web Portal for Fault Tolerant Methodology Application
Poupě, Petr ; Kaštil, Jan (referee) ; Mičulka, Lukáš (advisor)
This master's thesis deals with the development of web portal for the application of fault-tolerant methodologies. It introduces the issue of fault-tolerant systems and analyze system requirements, that have users working in this field. It describes the development cycle from analysis and specification of application system design through to implementation and testing part. More thoroughly it is focusing above design portal that provides a comprehensive and versatile solution to the problem that leads to the final implementation of this portal. This realization is part of the thesis.
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Methodology of highly reliable systems design
Straka, Martin ; Gramatová, Elena (referee) ; Racek, Stanislav (referee) ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
|
|
|
Methodology of highly reliable systems design
Straka, Martin ; Kotásek, Zdeněk (advisor)
In the thesis, a methodology alternative to existing methods of digital systems design with increased dependability implemented into FPGA is presented, new features which can be used in the implementation and testing of these systems are demonstrated. The research is based on the use of FPGA partial dynamic reconfiguration for the design of fault tolerant systems. In these applications, the partial dynamic reconfiguration can be used as a mechanism to correct the fault and recover the system after the fault occurrence. First, the general principles of diagnostics, testing and digital systems dependability are presented including a brief description of FPGA components and their architectures. Next, a survey of currently used methods and techniques used for the design and implementation of fault tolerant systems into FPGA is described, especially the methods used for fault detection and localization, their correction, together with the principles of evaluating fault tolerant systems design quality. The most important part of the thesis is seen in the description of the design methodology, implementation and testing of fault tolerant systems implemented into FPGAs which uses SRAMs as the configuration memory. First, the methodology of developing and automated checker components design for digital systems and communication protocols is presented. Then, a reference architecture of a dependable system implemented into FPGA is demonstrated including several fault tolerant architectures based on the use of partial dynamic reconfiguration as the mechanism of fault correction and the recovery from it. The principles of controlling the reconfiguration process are described together with the description of the test platform which allows to test and verify the design of fault tolerant systems based on the methodology presented in the thesis. The experimental results and the contribution of the thesis are discussed in the conclusions.
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Web Portal for VHDL Core Generator
Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
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Web Portal for Fault Tolerant Methodology Application
Poupě, Petr ; Kaštil, Jan (referee) ; Mičulka, Lukáš (advisor)
This master's thesis deals with the development of web portal for the application of fault-tolerant methodologies. It introduces the issue of fault-tolerant systems and analyze system requirements, that have users working in this field. It describes the development cycle from analysis and specification of application system design through to implementation and testing part. More thoroughly it is focusing above design portal that provides a comprehensive and versatile solution to the problem that leads to the final implementation of this portal. This realization is part of the thesis.
|
|
|
Automatic Construction of Checking Circuits Based on Finite Automata
Matušová, Lucie ; Strnadel, Josef (referee) ; Kaštil, Jan (advisor)
Cílem této práce bylo studium aktivního učení automatů, navržení a implementace softwarové architektury pro automatickou konstrukci hlídacího obvodu dané jednotky implementované v FPGA a ověření funkčnosti hlídacího obvodu pomocí injekce poruch. Hlídací obvod, tzv. online checker, má za úkol zabezpečovat danou jednotku proti poruchám. Checker je konstruován z modelu odvozeného pomocí aktivního učení automatů, které probíhá na základě komunikace se simulátorem. Pro implementaci učícího prostředí byla použita knihovna LearnLib, která poskytuje algoritmy aktivního učení automatů a jejich optimalizace. Byla navržena a implementována experimentální platforma umožňující řízenou injekci poruch do designu v FPGA, která slouží k otestování checkeru. Výsledky experimentů ukazují, že při použití checkeru a rekonfigurace je možné snížit chybovost designu o více než 98%.
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